A Test Architecture for System-on-a-Chip
نویسندگان
چکیده
This paper proposes a configurable TAM-Bus, a P1500 compliant Test Access Mechanism (TAM), and the TAMBus controller (TAM-controller) that is interfaced with JTAG at chip level of chip. All IP (Intellectual Property) cores’ test can be controlled through the TAP under the control of the TAM-controller. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The overhead increases only 0.17% due to TAM. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.
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تاریخ انتشار 2003